When thick (e.g. >5 μm) and stiff (high E-modulus/high yield stress) metallization stacks such as thick Cu, Al and Au power metals are introduced into a semiconductor device e.g. to enable particular interconnect solutions or improve thermal performance, high stresses occur near any film-terminating free-edge of the metal layer as a result of any sufficiently large temperature change. Such stresses occur due to the mismatch in the coefficients of thermal expansion (CTE) between the metal film and the underlying substrate (e.g. semiconductor materials or interlevel dielectrics). Temperature changes can occur during device processing (e.g. during cool-down to room temperature after an annealing step) or during use of the final device (e.g. power dissipation during switching operation under overload conditions). Free edges are created by the requirement of a patterned power metallization having defined lines and plates of limited size.
Whenever tensile stresses occur below the metal edge and hence in the substrate (e.g. SiO2- or Si3N4-based interlevel dielectrics, or the semiconductor substrate itself), cracks can result in the underlying brittle layers. This is in general the case during cool-down phases, e.g. from annealing at typically 400° C. down to room-temperature, if the CTE of the film is larger than that of the substrate, which is practically always the case.
To avoid cracks during production, either the temperature budget is reduced after deposition of the metal (e.g., to 300° C. anneal), or metals with reduced stiffness are utilized (e.g. aluminum with lower yield stress instead of harder copper). Both measures severely limit the technology, and may result in adverse side effects. Hence, improved crack-stop measures are desired.